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1 gsps quadrature digital upconverter w/18-bit iq data path and 14-bit dac preliminary technical data ad9957 rev. prf information furnished by analog devices is believed to be a ccurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to chan ge without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2006 analog devices, inc. all rights reserved. features 1gsps internal clock speed (up to 400mhz analog out) integrated 1gsps 14-bit dac 250 mhz i/q data throughput rate phase noise C123 dbc/hz (400 mhz carrier) excellent dynamic performance >80 db narrowband sfdr 8 programmable profiles for shift keying sin(x)/(x) correction (inverse sinc filter) reference clock multiplier internal oscillator for a single crystal operation software and hardware controlled power-down integrated ram phase modulation capability multichip synchronization easy interface to blackfin? sport interpolation factors from 4x to 252x test tone circuitry interpolation dac mode gain control dac internal divider allows references up to 2 ghz 1.8v & 3.3v power supplies 100 lead tqfp package applications hfc data, telephony & video modems wireless base station transmission broadband communications transmissions internet telephony general description the ad9957 functions as a universal i/q modulator and agile upconverter for communications systems where cost, size, power consumption and dynamic performance are critical. the ad9957 integrates a high speed direct digital synthesizer (dds), a high performance, high speed 14-bit digital to analog converter (dac), clock multiplier circuitry, digital filters and other dsp functions onto a single chip. it provides for base band up-conversion for data transmission in a wired or wireless communications system. the ad9957 is the third offering in a family of a quadrature digital upconverters (qducs), which includes the ad9857 and ad9856. it offers performance gains in operating speed, power consumption and spectral performance. unlike its predeces- sors, it also supports a 16-bit serial input mode for i/q base band data. the device can alternatively be programmed to op- erate as a single-tone sinusoidal source or as an interpolating dac. the reference clock input circuitry includes a crystal oscillator, a high speed divide-by-two input, and a low noise pll for mul- tiplication of the reference clock frequency. the user interface to the control functions includes a serial port easily configured to interface to the sport of the blackfin dsp and profile pins which enable fast and easy shift keying of any signal parameter (phase, frequency, and amplitude). figure 1: basic block diagram
ad9957 preliminary technical data rev. prf | page 2 of 38 table of contents electrical specifications ..................................... 3 absolute maximum ratings ............................... 6 pin configuration ............................................... 7 pin description.................................................... 8 modes of operation........................................... 10 quadrature modulation mode ........................... 10 blackfin interface mode .................................... 10 signal processing (qduc & bfi modes) ...........11 pdclk pin ................................................................ 11 txenable pin .............................................................. 11 input data assembler ................................................. 12 inverse cci filter....................................................... 13 fixed interpol ator (4x)................................................ 13 programmable interp olating f ilter ............................. 14 quadrature modulator ................................................ 15 dds core ................................................................... 15 inverse sinc filter .................................................... 15 output scale factor (osf) ......................................... 15 14-bit dac ................................................................ 15 auxiliary dac ........................................................... 16 interpolating dac mode .................................... 16 single-tone mode ................................................ 17 amplitude scale factor (asf) ................................... 17 i/o_update pin....................................................... 17 refclk input.................................................. 19 refclk pll...................................................... 19 refclk pll with crystal................................ 19 refclk: external interface..............................19 serial programming.......................................... 21 control interface?serial i/o..............................21 general operation of the serial interface..........21 instruction byte ....................................................22 serial interface port pin description..................22 msb/lsb transfers .............................................22 ram io via serial port .......................................23 ram control modes .............................................23 baseband input scaling with ram.....................23 i and q input data from ram................................23 register map and descriptions......................... 24 register map .................................................24 register descriptions ............................32 control function regi ster #1 (cfr1) ........................32 control function regi ster #2 (cfr2) ........................33 control function regi ster #3 (cfr3) ........................35 auxilliary dac cont rol register ...............................36 io update rate register.............................................36 qduc ram segment registers (qrsr0, qrsr1)..36 qrsrx<47:32> ram segment address ramp rate ................................................................................36 frequency tuning word register (ftw) ...................36 phase offset word register (pow)............................36 amplitude scale factor (asf) ...................................36 qduc profile x register (qduc-pxr)/..................36 single tone profile x register (st-pxr) ..................36 revision history revision pra (5/25/05): initial version of preliminary datasheet revision prb (9/30/05): register map, pinout, pin description added revision prc (12/06/05): register map completed, pinout updated. revision prd (2/27/06) further progress revision pre (3/31/06) incorporated marketing review comments
preliminary technical data ad9957 rev. prf | page 3 of 38 electrical specifications table 1. unless otherwise noted, avdd, dvdd = 1.8v 5%, dac_vdd, dvdd_i/o = 3.3 v 5%, r set = 10k, external reference clock frequency = 25 mhz. 40x reflck multiplier engaged. parameter min typ max unit ref clock input characteristics frequency range refclk multiplier disabled, divider disabled 1 1000 mhz refclk multiplier disabled, divider enabled 2000 mhz refclk multiplier enabled at 8 52.5 125 mhz refclk multiplier enabled at 64 6.5 35 mhz refclk multiplier enabled at 127 3.3 7.9 mhz xtal frequency on refclk inputs 20 30 mhz input capacitance 3 pf input impedance 1.5 k duty cycle 50 % duty cycle with refclk multiplier enabled 35 65 % refclk input voltage swing 100 1000 mv pk-pk refclk input power 1 C15 0 +3 dbm dac output characteristics full scale output current 10 20 30 ma gain error C10 +10 %fs output offset 0.6 a differential nonlinearity 1 lsb integral nonlinearity 2 lsb output capacitance 5 pf residual phase noise @ 1 khz offset, 400 mhz a out refclk multiplier disabled C123 dbc/hz refclk multiplier enable d @ 127 tbd dbc/hz refclk multiplier enabled @ 64 C105 dbc/hz refclk multiplier enabled @ 8 C115 dbc/hz ac voltage compliance range -0.5v 0.5v v spurious-free dynamic range (sfdr) fout = 50 mhz tbd dbc fout = 104 mhz tbd dbc fout = 209 mhz tbd dbc fout = 315 mhz tbd dbc fout = 403 mhz tbd dbc two tone intermodulation distortion (imd) fout = fout + 1.25 mhz fout = 50 mhz tbd dbc fout = 104 mhz tbd dbc fout = 209 mhz tbd dbc fout = 315 mhz tbd dbc fout = 403 mhz tbd dbc noise spectral density (nsd) single tone fout = 50 mhz tbd dbm / hz fout = 104 mhz tbd dbm / hz fout = 209 mhz tbd dbm / hz fout = 315 mhz tbd dbm / hz fout = 403 mhz tbd dbm / hz
ad9957 preliminary technical data rev. prf | page 4 of 38 parameter min typ max unit noise spectral density (nsd) continued eight tone, 500khz tone spacing fout = 50 mhz tbd dbm / hz fout = 104 mhz tbd dbm / hz fout = 209 mhz tbd dbm / hz fout = 315 mhz tbd dbm / hz fout = 403 mhz tbd dbm / hz modulator characteristics (260mhz a out input data: 10ms/s, qpsk, 4x oversampled i/q offset 55 65 db error vector magnitude 0.4 1 % input data: 10ms/s gmsk 4x oversampled i/q offset tbd tbd db error vector magnitude tbd tbd % input data: 10ms/s 256-qa m 4x oversampled i/q offset tbd tbd db error vector magnitude tbd tbd % adjacent channel leakage ratio (aclr) wcdma with 3.84mhz bw, 5mhz channel spacing fdac=1gsps, fout=200mhz 79 db fdac=1gsps, fout=400mhz 74 db timing characteristics parallel data bus maximum frequency 250 ms/s minimum txenable pulse width low 2 ns minimum txenable pulse width high 2 ns minimum data setup time (txenable to pdclk) 4 ns minium data hold time (pdclk risi ng edge to data change) 0 ns serial control bus maximum frequency 25 mbps minimum clock pulse width low 7 ns minimum clock pulse width high 7 ns maximum clock rise/fall time 2 ns minimum data setup time dvdd_i/o = 3.3 v 3 ns minimum data hold time 0 ns maximum data valid time 25 ns wake-up time 2 minimum reset pulse width high 5 sysclk cycles3 i/o update, ps0, ps1 to syncclk setup time dvdd_i/o = 3.3 v 4 ns i/o update, ps0, ps1 to syncclk hold time 0 ns latency i/o update to frequency change propa gation delay 24 sysclk cycles i/o update to phase offset change pr opagation delay 24 sysclk cycles i/o update to amplitude change propa gation delay 16 sysclk cycles cmos logic inputs logic 1 voltage 2.2 v logic 0 voltage 0.8 v logic 1 current 3 12 a logic 0 current 12 a input capacitance 2 pf
preliminary technical data ad9957 rev. prf | page 5 of 38 parameter min typ max unit cmos logic outputs (1 ma load) logic 1 voltage 2.8 v logic 0 voltage 0.4 v xtal output buffer specs logic 1 voltage 1.6 v logic 0 voltage tbd v output current tbd ma power consumption dvdd_i/o(3.3v) current consumption (qduc mode) ma dvdd(1.8v) current consumption (qduc mode) ma avdd(3.3v) current consumption (qduc mode) ma avdd(1.8v) current consumption (qduc mode) ma single tone mode 500 mw continuous modulation 255x interpolation tbd 1000 mw continuous modulation 4x interpolation tbd tbd mw burst modulation (25%) 255x in terpolation tbd tbd mw burst modulation (25%) 4x interpolation tbd tbd mw full-sleep mode tbd tbd mw inverse sinc filter power consumption 150 tbd mw 1 to achieve the best possible phase noise, the largest amplitude clock possible should be used. reducing the clock input ampli tude will reduce the phase noise performance of the device. 2 wake-up time refers to the recovery from analog power-down modes. 3 sysclk cycle refers to the actual clock frequency used on-chip by the dds. if the reference clock multiplier is used to multi ply the ex- ternal reference clock frequency, the sysclk frequency is the external frequency multiplied by the reference clock multiplicati on factor. if the reference clock multiplier and divider are not used, the sysclk frequency is the same as the external reference clock fr equency. figure 2 equivalent input/output (i/o) circuits
ad9957 preliminary technical data rev. prf | page 6 of 38 absolute maximum ratings table 2. parameter rating maximum unction temperature 150c avdd(1.8v), dvdd(1.8v) supplies 2 v avdd(3.3v), dvdd_i/o(3.3v) supplies 4v digital input voltage) 0.7 v to 4v digital output current 5 ma storage temperature 65c to 150c operating temperature 40c to 85c lead temperature (10 sec soldering) 300c a 38c/w c 15c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features pro- prietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electro- static discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
preliminary technical data ad9957 rev. prf | page 7 of 38 pin configuration
ad9957 preliminary technical data rev. prf | page 8 of 38 pin description pin # mnemonic i/o description 1, 24, 61, 72, 86, 87, 93, 97- 100 nc not connected. allow device pin to float. 2 pll_loop_filter i pll loop filter compensation pin. 3, 6, 89, 92 avdd (1.8v) i analog co re vdd: 1.8v analog supply. 74-77, 83 avdd (3.3v) i analog dac vdd: 3.3v analog supply. 17, 23, 30, 47, 57, 64 dvdd (1.8v) i digital core vdd: 1.8v digital supply. 11, 15, 21, 28, 45, 56, 66 dvdd_i/o (3.3v) i digital input/outp ut vdd: 3.3v digital supply. 4, 5, 73, 78, 79, 82, 85, 88, 96 agnd i analog ground. 13, 16,22, 29,46,58,62,63 65 dgnd i digital ground. 7 sync_in+ i digital input (rising edge active). synchron ization signal from external master to synchronize internal sub-clocks. 8 sync_in- i digital input (rising edge active). synchron ization signal from external master to synchronize internal sub-clocks. 9 sync_out+ o digitaloutput (rising edge active). synchroniz ation signal from internal device sub- clocks to synchronize external slave devices. 10 sync_out- o digitaloutput (rising edge active). synchroniz ation signal from internal device sub- clocks to synchronize external slave devices. 12 sync_smp_err o digital output (active high). sync sample er ror: a high on this pin indicates that the ad9957 did not receive a valid sync signal on sync_i+/sync_i-. 14 master _reset i digital input (active high). master reset: cl ears all memory elements and sets registers to default values. 18 ext_pwr_dwn i digital input (active high). external power do wn: a high level on this pin initates the currently programmed power down mode. please see the power down modes section of this document for further deta ils. if unused, tie to ground. 19 pll_lock o digital output (active high). pll_lock: a hi gh indicates the clock multiplier pll has acquired lock to the reference clock input. 20 cci_ovfl o digital output (active high). cci overflow: a high indicates a cci filter overflow. this pin will remain high until the cci overflow condition is cleared. 25-27, 31-39, 42-44, 48-50 d<17:0> i parallel data input bus (active high). these pins provide the interleaved 18 bit digital i & q vectors for the modu lator to upconvert. 42 sport i-data i in blackfin interface mode, th is pin serves as the i-data serial input. 43 sport q-data i in blackfin interface mode, th is pin serves as the q-data serial input. 40 pdclk/tsclk o digital output (clock) parallel data clock see signal processing section for details 41 txenable i digital input (active hi gh). transmit enable: see signal processing section for details 41 fs i in blackfin interface mode, this pin serves as the fs input, to receive the rfs output signal from the adsp bf533 51 isfc i digital input (active high). input scalin g function control: control for the ram amplitude scaling function. when this fu nction is engaged, a high sweeps the amplitude from the beginning ram address to the end. a low sweeps the amplitude from the end ram address to the beginning. 52-54 profile <2:0> i digital inputs (active high). profile sele ct pins: used to select one of eight phase/frequency profiles for th e dds core (single-tone or carrier tone). changing the state of one of these pins will transfer th e current contents of all i/o buffers to the corresponding registers. state changes sh ould be setup to the io_sync_clk pin. 55 sync_clk o digital output (clock). outp uts system clock/4. the i/ o_update and profile<2:0> pins should be setup to the rising edge of this signal.
preliminary technical data ad9957 rev. prf | page 9 of 38 59 i/o_update i digital input (active high). input/output update: a high on this pin transfers the contents of the i/o buffers to the corresponding internal registers. 60 osk i digital input (active high). output shaped keying: when the osk features (manual or automatic), this device controls the osk function. in manual mode, it toggles the multiplier between 0 (low) and the progra mmed amplitude scale factor (high). in automatic mode, a low sweeps the ampli tude down to zero, a high sweeps the amplitude up to the amplitude scale factor. 67 sdio i/o digital input/output (active high ). serial data inp ut/output: this pin can be either uni- directional or bidirectiona l (default), depending on configuration settings. in bidirectional serial port mode, this pin acts as the serial data input and output. in unidirectional, it is an input only. 68 sdo o digital output (active high). se rial data output: this pinis only active in unidirectional serial data mode. in this mode, it function s as the output. in bi directional mode, this pin is not operational and should be left floating. 69 sclk o digital clock (rising edge on write, falling ed ge on read). serial data clock: this pin provides the serial data clock for the co ntrol data path. write operations to the ad9957 use the rising edge. readback operations from the ad9957 use the falling edge. 70 cs i digital input (active low) chip select: br inging this pin low enables the ad9957 to detect serial clock rising/falling edges. br inging this pin high will cause the ad9957 to ignore input on the serial data pins. 71 i/o_reset i digital input (active high) i/o reset: rather than resetting the entire device during a failed communication cycle, when brought hi gh this pin will reset the state machine of the serial port controller and clear any i/o buffers that have been written since the last i/o update. when unused, tie this pin to ground to avoid accidental resets. 80 iout o analog output (current mode): open so urce dac complementary output source. connect through 50 to agnd. 81 iout o analog output (current mode): open sour ce dac output source. connect through 50 to agnd. 84 dac_rset o analog reference pin: programs the dac output full scale reference current. attach a 10k resistor to agnd. 90 ref_clk i analog input(active high): reference clk inp ut. can be driven by either an external oscillator or a simple crystal when the internal oscillator is engaged. 91 ref_ clk i analog input(active high): reference clk input 94 xtal_out o analog output (active high). crystal outp ut: provides the output of the internal oscillators response to a crystal. 95 xtal_sel o crystal select: selects the reference clock input mode when using the on- chip pll. pulling this pin low allows the user to provide a reference clock input to the pll from an external source. pulling this pin high enables the on-chip xtal buffer and allows the user to drive the reference input clock with a crystal
ad9957 preliminary technical data rev. prf | page 10 of 38 modes of operation the ad9957 has three basic operating modes: ? quadrature modulation mode (default) ? interpolating dac mode ? single-tone mode the active mode is selected via the qduc operating mode bits (cfr1 <25:24>). the inverse sinc filter is available in all three modes. quadrature modu lation mode a block diagram of the ad9957 operating in the quadrature modulation mode is shown in figure 3. in quadrature modula- tion mode, both i and q data paths are active and the parallel data clock (pdclk) serves to synchronize the input of i/q data to the ad9957. one 18-bit i word and one 18-bit q word to- gether comprise one internal sample . each sample propagates along the internal data pathway in parallel fashion. the dds core provides a quadrature (sine and cosine) local oscillator signal to the quadrature modulator, where the i and q data are multiplied by the respective phase of the carrier and summed together, producing a quadrature-modulated data stream. this data stream is routed through inverse sinc filter (optionally) and the output scaling multiplier and then applied to the -bit dac which produces the quadrature-modulated analog output signal. note: the profile and ioupdate pins are also synchronous to the pdclk. dds cos( t+ ) sin( t+ ) da c (14 -b) ftw ci c (1x -63x) ci c (1x - 63x) halfband filters 18 paralleldata tim ing & control i/q in interna l clock timing & control pdcl k se r ia l i/o port programming registers 2 3 clock multiplier refclk refclk ra m halfband filters inv. cci inv. cci po w er dow n control da c rs et io ut i out 0 1 0 1 0 1 iq 0 3 2 1 0 1 x sin(x) txen aux dac (8-b) i q 2 0 1 2 pw 8 dac gain 2 2 ad9957 (4x) (4x) is qs is qs ftw pw osf osf inverse sinc filter quadrature modulator figure 3: quadrature modulation mode blackfin interface mode a subset of the quadrature modulation mode is the blackfin interface ( bfi ) mode, which is shown in figure 4. in this mode a separate i and q serial bit stream is applied to the base band data port. the serial input provides for 16-bit i and q words (unlike parallel operation, which uses 18-bit words). the blackfin interface mode includes an additional pair of half band filters in both the i and q signal paths, increasing the in- terpolation of the base band data by 4x relative to the normal quadrature modulation mode.
preliminary technical data ad9957 rev. prf | page 11 of 38 dds cos( t+ ) sin( t+ ) da c (14 -b) ftw cci (1x -63x) ci c (1x - 63x) halfband filters inte rna l cl ock timi ng & control pdclk seria l i/o port sc lk sdata programming registers 2 sreset profile 3 regu d clock multiplier refclk sy s cl k pl l lo c k refclk ra m halfband filters inv. cci inv. cci po w er down control power down da c rs et io ut i out 0 1 0 1 f o r m a t t e r cic ofl res et 0 1 iq cs 0 3 2 1 0 1 x sin(x) sync in txen aux dac (8-b) i q 2 0 1 2 c lock m ode pw 8 dac gain 2 sync o ut 2 os k (4x) (4x) is qs is qs ftw pw osf osf i in q in halfband filter s halfband filters (4x) (4x) serial data timing and control fixed interpolators programmable interpolators quadrature modulator inverse sinc filter figure 4: quadrature modulation mode -- blackfin interface signal processing (qduc & bfi modes) to better understand the operation of the ad9957 it is helpful to follow the signal path in quadrature modulation mode from the parallel data port to the output of the dac, examining the function of each block (refer to figure 4). all timing within the ad9957 is provided by the internal sys- tem clock (sysclk) signal, which is generated from the timing source provided to the refclk pins. pdclk pin the timing of input data supplied to the ad is easily facili- tated ith the pdclk output pin, hich serves as a data cloc timing source in qduc mode, pdclk controls the timing of the 1-bit parallel input port in bfi mode, pdclk controls the timing of the dual serial input port the pdclk is provided as a continuous cloc (ie, alays active) oever, even though the pdclk output is active by default, it can be disabled via the enable pdclk bit in the register map. in qduc mode, the ad9957 expects alternating i and q data words at the parallel port (see figure 5). each rising edge of pdclk captures one -bit word that is, two pdclk cycles per iq pair.. in bfi mode, the ad9957 expects two serial bit streams each segmented into -bit words with each rising edge of pdclk indicating a new bit. in either case, the output clock rate is f data as explained in the input data assembler section. txenable pin the rising edge of the txenable signal is used to synchronie the device while txenable is in the logic 0 state, the device ignores the data applied to the parallel port alloing the inter- nal data path to be flushed by forcing eros don the i and q data pathays on the rising edge of txenable, the device is ready for the first i ord the first i ord is latched into the device coincident ith the rising edge of pdclk the next rising edge of pdclk latches in a q ord, etc, until txenable is set to a logic 0 state by the user it is important that the user ensure an even number of pdclk intervals are observed during any given txenable period the device must capture both an i and a q sample before the data is processed along the signal chain. in bfi mode, operation of the txenable pin is similar except that instead of the rising edge marking the first i word, it marks the first i (and q) bit in a serial frame. it is important that the user ensure a multiple of pdclk cycles are observed during any given txenable period. the device must capture a full -bit i and q sample before the data is processed along the signal chain. the timing relationship between txenable, pdclk, and
ad9957 preliminary technical data rev. prf | page 12 of 38 data is shown in figure 5 and figure 6. t dh i 0 txenable pdclk d<13:0> q n i n q 1 i 1 q 0 01018-c-021 t dh t ds t ds figure 5. 18-bit parallel port timing diagram?quadrature modulation mode table 3. parallel data bus timing symbol definition minimum t ds data setup time 4 ns t dh data hold time 0 ns figure 6: dual serial i/q bits tream timing diagram bfi mode table 4: serial data bus timing symbol definition minimum t ds data setup time tbd t dh data hold time tbd input data assembler the input to the ad is an 1-bit parallel data port in quad- rature modulation mode (or a dual serial data port in the bfi mode) it is assumed that to consecutive 1-bit ords repre- sent the real (i) and imaginary (q) parts of a complex number that has the form iq the 1-bit ords are supplied to the input of the ad at a rate of r f f sysclk data 2 = r f f sysclk data =
preliminary technical data ad9957 rev. prf | page 13 of 38 delivered to the input of the ad9957 may be formatted as either twos-complement or unsigned binary (see the data format bit in the register map). furthermore, in bfi mode, the order of the bit sequence can be set to either sb first or lsb first (via the blackfin bit order bit in the register map). inverse cci filter the inverse cci (cascaded comb integrator) filter precompen- sates the data to offset the slight attenuation gradient imposed by the cci filter (see the programmable (2 to 3) cci inter- polating filter section) data entering the first half-band filter occupies a maximum band idth of one-half f iq as defined by nyquist (here f iq is the sample rate at the input of the first half-band filter) this is shon graphically in figure if the cci filter is employed, the inband attenuation gradient could pose a problem for those applications requiring an ex- tremely flat pass band for example, if the spectrum of the data as supplied to the ad occupies a significant portion of the one-half f data region, the higher frequencies of the data spec- trum receives slightly more attenuation than the loer frequen- cies (the orst-case overall droop from f0 to f data is 0 db) the inverse cci filter has a response characteristic that is the inverse of the cci filter response over the f iq region figure cci filter response the product of the to responses yields in an extremely flat pass band (00 db over the base band nyquist band idth), thereby eliminating the inband attenuation gradient introduced by the cci filter the cost is a slight attenuation of the input signal of approximately 0 db for a cci interpolation rate of 2 and 0 db for interpolation rates of 3 to 3 the inverse cci filter can be bypassed using the appropriate bit in the register map even if it is enabled, it is automatically by- passed if the cci interpolation rate is 1 when the inverse cci filter is bypassed, poer to the stage is turned off to reduce poer consumption fixed interpolator (4x) this bloc is a fixed 4 rate interpolator it is implemented as a cascade of to half-band filters together, the to half-band filters provide a factor of four increase in the sampling rate, hile preserving the spectrum of the base band signal applied at the input both half-band filters are linear phase filters, so that virtually no phase distortion is introduced ithin the pass band of the filters their combined insertion loss is 001 db, thus preserving the relative amplitude of the input signal the half-band filters are designed so that their composite per- formance yields a usable pass band of 40 of the input sample rate (02 on the frequency scale belo) within that pass band, the ripple does not exceed 0002 db the stop band extends from 0 to 200 of the input sample rate (03 to 10 on the frequency scale) and offers a minimum of db attenuation figure and figure sho the composite response of the to half-band filters frequency 0 0.2 0.4 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.3 0.2 ?85 sample rate 01018-c-024 figure 8. half-band 1 and 2 frequency response; frequency relative to hb1 output sample rate 0 0 0.05 0.10 0.15 0.20 0.25 0.010 0.008 0.006 0.004 0.002 ?0.002 ?0.004 ?0.006 ?0.008 ?0.010 relative frequency (hb1 output sample rate = 1) gain (db) 01018-c-025 figure 9. combined half-band 1 and 2 pass band detail; frequency relative to hb1 output sample rate
ad9957 preliminary technical data rev. prf | page 14 of 38 knowledge of the frequency response of the half-band filters is essential to understanding their impact on the spectral proper- ties of the input signal. this is especially true when using the quadrature modulator to upconvert a base band signal contain- ing complex data symbols that have been pulse shaped. to better understand this concept, consider that a complex symbol is represented by a real (i) and imaginary (q) compo- nent. thus, two digital words are required to represent a single complex sample of the form: i+jq. the sample rate associated with a sequence of complex symbols will be referred to as f sym- bol . if pulse shaping is applied to the symbols, then the sample rate must necessarily be increased by some integer factor, m (a consequence of the pulse shaping process). this new sample rate with be referred to as f iq , and is related to the symbol rate by: symbol iq mf f = note: this rate is not to be confused with the rate at which parallel data is supplied to the ad9957( f data ), which is equal to 2f iq . typically, pulse shaping is applied to the base band symbols via a filter having a raised cosine response. in such cases, an excess band width factor () is used to modify the band width of the data where 0 . a value of 0 causes the data band width to correspond to f sbol , while a value of causes the data band width to be extended to f sbol . figure 0 illustrates the rela- tionship between , the band width of the raised cosine re- sponse, and the response of the first half-band filter. f ?f symbol nyquist band width f = 0 = 0.5 = 1 f ? f iq f iq f symbol ?f symbol f symbol 2f symbol sample rate for 2x oversampled pulse shaping 4f symbol 2f iq input sample rate of 1 st half-band filter output sample rate of 1 st half-band filter 2f symbol 3f symbol typical spectrum of a random symbol sequence raised cosine spectral mask half-band filter response 0.4f iq figure 10. effect of the excess band width factor ( programmable interpolating filter the programmable interpolator is implemented as a cci filter ith a lo-pass frequency characteristic it is programmable by a -bit control ord, giving a range of 2 to 3 interpolation
preliminary technical data ad9957 rev. prf | page 15 of 38 the programmable interpolator is bypassed when programmed for an interpolation factor of 1. when bypassed, power to the stage is removed and the inverse cci filter (see above) is also bypassed, because its compensation is not needed in this case. the output of the programmable interpolator is the data from the 4 interpolator further upsampled by the cci filter, ac- cording to the rate chosen by the user. this results in the input data being upsampled by a factor of 8 to 252 in steps of 4. the transfer function of the cci interpolating filter is 5 1 0 ) 2 ( ) ( ? ? ? ? ? ? = ? = ? r k fk j e f h () where r is the programmed interpolation factor, and f is the frequency relative to ssclk. quadrature modulator the digital quadrature modulator stage shifts the frequency of the base band spectrum of the incoming data stream up to the desired carrier frequency (this process is known as up- conversion ). at this point the base band data, which was delivered to the device at an iq sample rate of f iq , has been upsampled to a rate equal to the frequency of ssclk, making the data sampling rate equal to the sampling rate of the carrier signal. the frequency of the carrier signal is controlled numerically by a direct digital synthesier (dds). the dds generates the de- sired carrier frequency from the internal reference clock (ssclk) very precisely. the carrier is applied to the i and q multipliers in quadrature fashion (90 phase offset) and summed, yielding a data stream that represents the quadrature modulated carrier . the modulation is done digitally avoiding the phase offset, gain imbalance and crosstalk issues commonly associated with ana- log modulators. note that the modulated signal is a number stream sampled at the rate of ssclk, the same rate at which the dac is clocked. the orientation of the modulated signal with respect to the carrier is controlled by a spectral invert bit. this bit resides in each of the four profile registers. by default, the time domain output of the quadrature modulator takes the form: () () t t q t t i ? () () t t q t t i + dds core the direct digital synthesier (dds) bloc generates the sine and cosine carrier reference signals that digitally modulate the i/q data the dds output is tuned using registers accessed via the serial programming port this allos for both precise tun- ing of the carrier frequency and the ability to change frequency instantaneously the equation relating output frequency (f out ) of the ad digital modulator to the frequency tuning ord (ftw) and the system cloc (f ssclk ) is sysclk out f ftw f ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = sysclk out f f round ftw 32 2 (5) the round() function means to round the result to the nearest integer. for example, for f out h and f ssclk 22.88 h, then ft ,33,053,87 (55aaaab hex). inverse sinc filter the sampled carrier data stream is the input to the digital-to- analog converter (dac) integrated onto the ad the dac output spectrum is shaped by the characteristic sin(x)/x (or sinc) envelope, due to the intrinsic ero-order hold effect associated ith dac-generated signals the sinc envelope is ell non and can be compensated for this envelope restora- tion function is provided by the inverse sinc filter that pre- cedes the dac by default, the filter is bypassed it is enabled via a bit in the register map the inverse sinc function is im- plemented as an fir filter its response characteristic is the exact inverse of the sinc response the inverse sinc filter pre- distorts the data prior to its arrival at the dac the correction is only accurate for output frequencies up to approximately 40 of ssclk note: the inverse sinc fi lter exhibits ~3.5db of insersion loss . output scale factor (osf) output amplitude is controlled using an -bit digital multiplier the -bit multiplier value is called the output scale factor (osf) and is programmed via the appropriate control registers it is available for each of the eight profiles the lsb eight is 2 , hich yields a multiplier range of 0 to 121 (2-2 - ) the gain extends to nearly a factor of 2 to provide a means to over- come the intrinsic loss through the modulator hen operating in the quadrature modulation mode note: programming the 8-bit multiplier to unity gain (80h) bypasses the stage and reduces power consumption . 14-bit dac the ad incorporates an integrated 14-bit current-output dac the output current is delivered as a balanced signal using
ad9957 preliminary technical data rev. prf | page 16 of 38 two outputs. the use of balanced outputs reduces the amount of common-mode noise at the dac output, increasing signal-to- noise ratio. an external resistor (r set ) connected between the dac_r set pin and the dac ground (agnd_dac) establishes a reference current. the full-scale output current of the dac (i out ) is produced as a scaled version of the reference current (see the auxiliary dac section that follows). proper attention should be paid to the load termination to keep the output voltage within the specified compliance range, as voltages developed beyond this range will cause excessive distortion and might even damage the dac output circuitry. auxiliary dac the full scale output current of the main dac (i out ) is con- trolled by an -bit auxiliary dac an -bit code ord stored in the appropriate register map location sets i out according to the folloing equation ? ? ? ? ? ? + = code r i set out (6) where r set is the value of the r set resistor (in ohms) and code is the 8-bit value supplied to the auxiliary dac (default is 127). for example, with r set =10,000 and code=127, then i out =20.07ma. interpolating dac mode a block diagram of the ad9957 operating in the interpolating dac mode is shown in figure 11; grayed out items are inactive. in this mode, the q data path, dds and modulator are all dis- abled; only the i data path is active. cci (1x -63x) dds cos( t+ ) sin( t+ ) dac (14-b) halfband filters (4x) 18 parallel data timing & control i/q in internal clock timing & control pdclk clock multiplier refclk pll lock refclk halfband filters (4x) inv. cci inv. cci dac rset iout iout 0 1 0 1 de-interleaver reset 0 1 ad9957: interpolating dac mode 0 3 2 1 0 1 x sin(x) txen 2 0 1 2 clock mode osf aux dac (8-b) 8 dac gain serial i/o port sclk sdata programming registers 2 sreset profile 3 regud ram power down control power down cci ofl i q cs sync in f 2 sync out 2 g osk ftw 0 1 freq. ramp logic pw f 0 1 r r cci (1x -63x) q i i figure 11: interpolating dac mode as in the quadrature modulation mode, the pdclk pin func- tions as a clock which serves to synchronize the input of data to the ad9957. the pdclk rate is given below. note that it oper- ates at a rate that is half of that for the quadrature modulation mode. r f f sysclk data 4 = input data assembler section. each pdclk rising edge latches a data word into the i data path.
preliminary technical data ad9957 rev. prf | page 17 of 38 the timing relationship between txenable, pdclk, and data is shown in figure 12. t dh i 0 txenable pdclk d<13:0> i k i k? 1 i 3 i 2 i 1 01018-c-022 t dh t ds t ds figure 12. 18-bit parall el port timing diagram?interpolating dac mode single-tone mode dds cos( t+ ) sin( t+ ) dac (14-b) halfband filters (4x) 18 parallel data timing & control i/q in internal clock timing & control pdclk clock multiplier refclk sysclk pll lock refclk halfband filters (4x) inv. cci inv. cci dac rset iout iout 0 1 0 1 de-interleaver reset 0 1 ad9957: single-tone mode 0 3 2 1 0 1 x sin(x) txen i q 2 0 1 2 clock mode aux dac (8-b) 8 dac gain serial i/o port sclk sdata programming registers 2 sreset profile 3 regud ram power down control power down cci ofl iq cs sync in f sync out 2 g osk 2 ftw cci (1x -63x) cci (1x - 63x) 0 1 freq. ramp logic pw f 0 1 r r i q sweep figure 13: single-tone mode a block diagram of the ad9957 operating in the single-tone mode is shown in figure 13; grayed out items are inactive. in this mode, both i and q data paths are disabled from the 18-bit parallel data port up to and including the modulator. the in- ternal dds core produces a signal whose frequency depends on the programmed tuning word. the user may select either the cosine (default) or sine output of the dds. the sinusoid at the dds output can be scaled via a 14-bit amplitude scale factor (asf) and optionally routed through the inverse sinc filter. amplitude scale factor (asf) output amplitude is controlled by a 14-bit digital multiplier called the amplitude scale factor (asf), hich is programmed via the appropriate control registers it is available for each of the eight profiles the lsb eight is 2 14 , hich yields a multi- plier range of 0 to 13443 (1-2 -14 ) in addition to the ability to generate single tone signals in this mode, the ad can also provide 2-, 4-, or -level modula- tion of frequency, phase, or amplitude by means of the eight available profile registers and the profile02 pins i/o_update pin in the single-tone mode, the i/o_update pin serves as a sig- nal update strobe frequency, phase and amplitude control ords for the dds are programmed via the serial port (see the control register description) the serial port is an asynchro- nous interface the i/o_update pin allos for synchronia- tion of the ad output ith external circuitry hen ne frequency, phase, or amplitude values are programmed into the on-chip profile registers a rising edge initiates transfer of the
ad9957 preliminary technical data rev. prf | page 18 of 38 programmed data for the selected profile (see the profile sec- tion), thus resuming the frequency synthesis process with the new values. note: the transfer of programmed data from the programming registers to the internal hardware is also accom- plished by switching between profiles .
preliminary technical data ad9957 rev. prf | page 19 of 38 refclk input the ad9957 supports a few methods for generating the internal system clock. an on-chip oscillator circuit is available for initi- ating a low frequency reference signal by connecting a crystal to the clock input pins. the system clock may also be generated using the internal, pll-based reference clock multiplier, allow- ing the part to operate with a low frequency clock source while still providing a high update rate for the dds and dac. using the clock multiplier can impact the output phase noise charac- teristics - for best phase noise performance, a clean, stable clock with a high slew is required. a clock of frequency higher than the maximum allowable clock rate can be used if the refclk input divide by 2 is enabled using the refclk input divider enable bit cfr3<15>. refclk pll enabling the pll (via the pll enable bit, cfr3<8>) allows multiplication of the reference clock frequency. the multiplica- tion factor in the clock multiplier is set by bits cfr3 <7:1> with values ranging from 8 to 10 and 12 to 127 (decimal). pro- gramming cfr3<7:1> for values less than 8 or 11 is not valid and will cause unpredictable device performance. the system clock rate with the clock multiplier enabled is equal to the refer- ence clock rate times the multiplication factor. when using the clock multiplier, the correct vco and charge pump current must be selected. the vco range is selected by programming the vco sel bits, cfr3 <26:24>.. the charge pump current is programmed through the icp bits, cfr3<21:19>. see the regis- ter map for tables showing the available settings whenever the pll clock multiplier is enabled or the multiplica- tion value changed, the pll must reacquire lock. once lock is achieved, the lock_detect signal will be output on pin 19. while the pll is out of lock, transmission in the qduc is gated off. refclk pll with crystal the on-chip oscillator for crystal operation is enabled using xtal_sel (pin 95). the xtal_sel pin is an analog input, operating on 1.8v logic. with the on-chip oscillator enabled, connecting an external crystal across the ref_clk and ref_clkb inputs produces a low frequency reference clock. the range of frequencies supported is listed in the specification table. a buffer outputs a regenerated refclk/crystal oscillator signal on the xtal_out pin (pin 94). harmonic interference effects may be mitigated using drv slew rate control bits cfr3<31:30>. table 5 summarizes the clock mode options. see the register table/map section for more detail. xtal_sel pin (95) cfr1<7:1> pll, bits = m pll enabled (cfr3<15> system clock (f sys clk ) min/max freq. range (mhz) high = 1.8 v logic 12 m 127, or 8 m 10 yes cfr3<15>=1 f sys clk = f osc m 500 < f sysclk < 1000 high = 1.8 v logic m < 8, m=11, or m > 127 no f sys clk = f osc 20 < f sysclk < 30 low 12 m 127 or 8 m 10 yes cfr3<15> = 1 f sys clk = f ref clk m 500 < f sysclk < 1000 low m < 8, m=11, or m > 127 no f sys clk = f ref clk 0 < f sys clk < 1000 table 5 clock mode options refclk: external interface the reference clock input circuitry has two modes of operation. the first mode configures it as an input buffer. in this mode, the reference clock must be ac-coupled to the input due to internal dc biasing. this mode supports either differential or single- ended configurations. if single-ended mode is desired, clkb (pin 91) should be decoupled to avdd or agnd via a 0.1 f capacitor. the next three figures exemplify common reference clock configurations for the ad9957. figure 14 the reference clock inputs can also support an lvpecl or pecl driver as the reference clock source. 1:1 balun clk pin 90 reference clock source clk pin 91 50 0.1 f 0.1 f 05252-032
ad9957 preliminary technical data rev. prf | page 20 of 38 figure 15 for external crystal operation, both clock inputs must be dc- coupled via the crystal leads and bypassed. figure 16 shows the configuration for using a crystal. figure 16 clk pin 90 clk pin 91 0.1 f 0.1 f lvpecl/ pecl driver termination 05252-033 clk pin 90 25mhz xtal clk pin 91 22pf 22pf 05252-034
preliminary technical data ad9957 rev. prf | page 21 of 38 serial programming control interface?serial i/o the ad9957 serial port is a flexible, synchronous serial communi- cations port allowing easy interface to many industry standard microcontrollers and microprocessors. the serial i/o is compatible with most synchronous transfer formats, including both the mo- torola 6905/11 spi and intel 8051 ssr protocols. the interface allows read/write access to all registers that configure the ad9957. msb first or lsb first transfer formats are supported. in addition, the ad9957?s serial interface port can be configured as a single pin i/o (sdio), which allows a two-wire interface or two unidirectional pins for in/out (sdio/sdo), which enables a three wire interface. two optional pins (ioreset and csb) enable greater flexibility for system design-in of the ad9957. with the ad9957, the instruction byte specifies read/write opera- tion and register address. serial operations on the ad9957 occur only at the register level, not the byte level due to the lack of byte address space in the instruction byte. for the ad9957, the serial port controller recognizes the register address in the instruction byte and expects that all bytes of that register will be accessed, otherwise, the serial port controller will be out of sequence for the next write routine. however, one way to write less bytes than required is to use the ioreset feature. the ioreset function can be used to abort an io operation and reset the pointer in the serial port controller. after an ioreset, the next byte will be the instruction byte. every byte that is written prior to the ioreset is preserved. partial bytes are not preserved. general operation of the serial interface there are two phases to a communication cycle with the ad9957. phase 1 is the instruction cycle, which is the writing of an instruc- tion byte into the ad9957, coincident with the first eight sclk rising edges. the instruction byte provides the ad9957 serial port controller with information regarding the data transfer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcoming data transfer is read or write and the serial address of the register being accessed the first eight sclk rising edges of each communication cycle are used to write the instruction byte into the ad9957. the remaining sclk edges are for phase 2 of the communication cycle. phase 2 is the actual data transfer between the ad9957 and the system con- troller. the number of bytes transferred during phase 2 of the communication cycle is a function of the register being accessed. for example, when accessing the control function register #2, which is four bytes wide, phase 2 requires that four bytes be trans- ferred. if accessing the amplitude scale factor register, which is two bytes wide, phase 2 requires that two bytes be transferred. after transferring all data bytes per the instruction, the communication cycle is completed. at the completion of any communication cycle, the ad9957 serial port controller expects the next 8 rising sclk edges to be the in- struction byte of the next communication cycle. all data input to the ad9957 is registered on the rising edge of sclk. all data is driven out of the ad9957 on the falling edge of sclk. the figures below are useful in understanding the general opera- tion of the ad9957 serial port. i 7 sdio instruction cycle data transfer cycle sclk cs i 6 i 5 i 4 i 3 i 2 i 1 i 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 01018-c-029 serial port writing timing?clock stall low d o7 instruction cycle data transfer cycle don't care i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 sdio s clk cs sdo d o6 d o5 d o4 d o3 d o2 d o1 d o0 01018-c-030
ad9957 preliminary technical data rev. prf | page 22 of 38 3-wire serial port read timing?clock stall low i 7 sdio instruction cycle data transfer cycle sclk cs i 6 i 5 i 4 i 3 i 2 i 1 i 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 01018-c-031 serial port write timing?clock stall high i 7 sdio instruction cycle data transfer cycle sclk cs i 6 i 5 i 4 i 3 i 2 i 1 i 0 d o7 d o6 d o5 d o4 d o3 d o2 d o1 d o0 01018-c-032 2-wire serial port read timing?clock stall high instruction byte the instruction byte contains the following information as shown in the table below: instruction byte information msb d6 d5 d4 d3 d2 d1 lsb r/w b x x a4 a3 a2 a1 a0 r/-wbbit 7 of the instruction byte determines whether a read or write data transfer will occur after the instruction byte write. logic high indicates read operation. logic zero indicates a write opera- tion. x, xbits 6 and 5 of the instruction byte are dont care. a4, a3, a2, a1, a0bits 4, 3, 2, 1, 0 of the instruction byte deter- mine which register is accessed during the data transfer portion of the communications cycle. serial interface port pin description sclk serial clock. the serial clock pin is used to synchronize data to and from the ad9957/10 and to run the internal state ma- chines. sclk maximum frequency is 10 mhz. csb chip select bar. active low input that allows more than one device on the same serial communications line. the sdo and sdio pins will go to a high impedance state when this input is high. if driven high during any communications cycle, that cycle is suspended until cs is reactivated low. chip select can be tied low in systems that maintain control of sclk. sdio serial data i/o. data is always written into the ad9957/10 on this pin. however, this pin can be used as a bi- directional data line. bit 7 of register address 0h controls the con- figuration of this pin. the default is logic zero, which configures the sdio pin as bi-directional. sdo serial data out. data is read from this pin for protocols that use separate lines for transmitting and receiving data. in the case where the ad9957/10 operates in a single bi-directional i/o mode, this pin does not output data and is set to a high impedance state. ioreset synchronizes the i/o port state machines without affecting the addressable registers contents. an active high input on the ioreset pin causes the current communication cycle to abort. after ioreset returns low (logic 0) another communication cycle may begin, starting with the instruction byte write. msb/lsb transfers the ad9957/10 serial port can support both most significant bit (msb) first or least significant bit (lsb) first data formats. this functionality is controlled by the control function register 1 <0> bit. the default value of control function register 1 <0> bit is low (msb first). when control function register 1 <0> bit is set high, the ad9957/10 serial port is in lsb first format. the instruction byte must be written in the format indicated by control function register 1 <0> bit. that is, if the ad9957/10 is in lsb first mode, the instruction byte must be written from least significant bit to most significant bit. for msb first operation, the serial port controller will generate the most significant byte (of the specified register) address first fol- lowed by the next lesser significant byte addresses until the io op-
preliminary technical data ad9957 rev. prf | page 23 of 38 eration is complete. all data written to (read from) the ad9957/10 must be (will be) in msb first order. if the lsb mode is active, the serial port controller will generate the least significant byte address first followed by the next greater significant byte addresses until the io operation is complete. all data written to (read from) the ad9957/10 must be (will be) in lsb first order. ram io via serial port accessing the ram via the serial port is identical to any other se- rial io operation except that the number of bytes transferred is determined by the address space between the beginning address and the final address as specified in the current ram segment control word (rscw). the final address describes the most sig- nificant word address for all io transfers and the beginning address specifies the least significant address. ram io supports msb/lsb first operation. when in msb first mode, the first data byte will be for the most significant byte of the memory address described by the final address with the remaining three bytes making up the lesser significant bytes of that address. the remaining bytes come in most significant to least significant, destined for ram addresses generated in descending order until the final four bytes are written into the address specified as the beginning address. when in lsb first mode, the first data byte will be for the least significant byte of the memory (specified by the beginning address) with the remaining three bytes making up the greater significant bytes of that address. the remaining bytes come in least significant to most significant, destined for ram addresses generated in ascending order until the final four bytes are written into the memory address described by the final address. of course, the bit order for all bytes is least significant to most significant first when in the lsb first bit is set. when the lsb first bit is cleared (default) the bit order for all bytes is most significant to least sig- nificant. ram control modes baseband input scaling with ram in qduc and dac interpolation modes, the baseband data may be scaled via the 18x16 bit multiplier(s)(is,qs), whose multiplicand is driven by the ram. this function offers the customer a means of performing an arbitrary amplitude ramp up/down of the base- band data. the ramp profile is generated at the input sample rate and interpolated up to the dac sample rate through the baseband signal chain in the same manner as the i/q data, significantly re- ducing power dissipation. in this configuration, the 32-bit ram words are partitioned into two 16-bit words. the data being used as a scale factor for the i/q words supplied by the user to the 18-bit parallel port. the ram words are accessed at the iq sample rate (output rate of the data assembler logic). the scale factor, driven from the ram, is an unsigned value. all zeros multiplies the baseband data by 0 (decimal) and ffffh mul- tiplies the baseband data by nearly 1.0 (0.ffff equates to .99985). invoke the input data scaling mode using the ram enable bit and the ram qduc evaluation bit, while in qduc or interpolating dac mode. the input scale factor control (isfc) pin is used to start and stop the ram controller. two 48-bit registers are dedi- cated for controlling the ram segmentation and ramp rates. see the qduc ram segment #0 (qrsr0) and the qduc ram seg- ment #1 (qrsr1) registers in the register map. i and q input data from ram in the qduc mode, the ram can be configured to supply iq data. the ram is partitioned as two 16-bit words. the two words are routed to the baseband data pathway. one word is routed to the "i" channel and the other word is routed to the "q" channel. this will allow the user to easily generate a customized modulation waveform composed of up to 1024 i/q samples without the need for external support cir- cuitry to supply data to the parallel input port. this feature is an attempt to simplify the user?s design/debug process when the device is incorporated into a new product design. synchronizing multiple ad9957s devices the ad9957 product includes circuitry that enables multiple ad9957 products to be automatically synchronized to one an- other. multiple devices are considered synchronized when the state of the clock generation state machines are identical for all parts. multiple part synchronization can be achieved by a sim- ple connection of lvds outputs on the master device to the lvds inputs of the slave device(s). devices are configured as master and slaves through programming bits, accessible via the serial port. pipeline matching of the ftw, phase offset, and output scaling the ad9957 offers a feature that enables the simultaneous applica- tion of changes in frequency, phase and amplitude to be applied in a manner that allows these parameters to be synchronized to the specific pipe delays of the preceding logic blocks. this feature is controllable via the serial port and is activated by writing the match pipe delays active bit to a logic one. output shaped on-off keying modes auto and manual shaped on-off keying modes are supported. auto mode generates a linear scale factor at a rate determined by the amplitude ramp rate register (arr), controlled by an exter- nal pin (osk). manual mode allows the user to directly control the output amplitude by writing the scale factor value into the am- plitude scale factor register (asfr).
ad9957 preliminary technical data rev. prf | page 24 of 38 register map and descriptions register map register name (serial address) bit range bit 7 (msb) bit 6 bit 5 bit4 bit 3 bit 2 bit 1 bit 0 (lsb) default va lu e or profile <31:24> ram enable open ram qduc evaluation open qduc operating mode 00h <23:16> manual osk external control inverse sinc filter enable clear cci internal profile control enable sine output 00h <15:8> open auto-clear phase accum open clear phase accum load arr @ i/o update output shaped keying enable auto output shaped keying 00h control function register 1 cfr1 (00h) <7:0> digital power down dac power down clock input power down aux dac power down external power down mode auto power down enable sdio input only lsb first 00h <31:24> blackfin interface mode active blackfin bit order black fin early frame sync enable open 00h <23:16> internal io update active enable io update clock open read effective ftw 40h <15:8> io update rate control pdclk rate control data format enable pdclk pdclk clock invert txenable invert q first data pairing 08h control function register 2 (cfr2) (01h) <7:0> matched latency enable data assembler hold last va lu e sync sample error mask open fm gain 20h <31:24> drv0<1:0> open vco sel <2:0> 1fh <23:16> open icp<2:0> open 3fh <15:8> refclk input divider disable open pll enable 40h control function register 3 (cfr3) (02h) <7:0> n:<6:0> open 00h <31:24> open 00h <23:16> open 00h <15:8> open 00h auxilliary dac control register (03h) <7:0> fsc<7:0> ffh
preliminary technical data ad9957 rev. prf | page 25 of 38 register name (serial address) bit range (internal address) bit 7 (msb) bit 6 bit5 bit 4 bit 3 bit 2 bit 1 bit 0 default va lu e or profile <31:24> io update rate <31:24> ffh <23:16> io update rate <23:16> ffh <15:8> io update rate <15:8> ffh io update rate register (04h) <7:0> io update rate <7:0> ffh <47:40> ram segment 0 address ramp rate <15:8> isfc0 <39:32> ram segment 0 address ramp rate <7:0> isfc0 <31:24> ram segment 0 final address <9:2> isfc0 <23:16> ram segment 0 final address <1:0> open isfc0 <15:8> ram segment 0 beginning address <9:2> isfc0 qduc ram segment register 0 (05h) <7:0> ram segment 0 beginning address <1:0> open ram segment 0 mode control <2:0> isfc0 <47:40> ram segment 1 address ramp rate <15:8> isfc1 <39:32> ram segment 1 address ramp rate <7:0> isfc1 <31:24> ram segment 1 final address <9:2> isfc1 <23:16> ram segment 1 final address <1:0> open isfc1 <15:8> ram segment 1 beginning address <9:2> isfc1 qduc ram segment register 1 (06h) <7:0> ram segment 1 beginning address <1:0> open ram segment 1 mode control <2:0> isfc1 <31:24> frequency tuning word <31:24> 00h <23:16> frequency tuning word <23:16> 00h <15:8> frequency tuning word <15:8> 00h ftw register (07h) <7:0> frequency tuning word <7:0> 00h <15:8> phase offset word <15:8> 00h pow register (08h) <7:0> phase offset word <7:0> 00h <31:24> amplitude ramp rate <15:8> 00h <23:16> amplitude ramp rate <7:0> 00h <15:8> amplitude scale factor <13:6> 00h asf register (09h) <7:0> amplitude scale factor <5:0> amplitude ramp rate speed control <1:0> 00h
ad9957 preliminary technical data rev. prf | page 26 of 38 register name (serial address) bit range (internal address) bit 7 (msb) bit 6 bit5 bit 4 bit 3 bit 2 bit 1 bit 0 default va lu e <31:24> sync window delay <3:0> sync enable sync driver enable sync polarity internal sync loop enable 00h <23:16> system clock offset<5:0> open 00h <15:8> output sync pulse delay <4:0> open 00h <7:0> input sync pulse delay <4:0> open 00h <23:16> falling sweep ramp rate word <7:0> 00h <15:8> rising sweep ramp rate word <15:8> 00h multi-chip sync register (0ah) <7:0> rising sweep ramp rate word <7:0> 00h <63:56> cci interpolation rate spectral invert inverse cci bypass 000 <55:48> output scale factor 0 000 <47:40> phase offset word 0 <15:8> 000 <39:32> phase offset word 0 <7:0> 000 <31:24> frequency tuning word 0 <31:24> 000 <23:16> frequency tuning word 0 <23:16> 000 <15:8> frequency tuning word 0 <15:8> 000 qduc profile 0 register (0eh) <7:0> frequency tuning word 0 <7:0> 000 <63:56> cci interpolation rate spectral invert inverse cci bypass 001 <55:48> output scale factor 1 001 <47:40> phase offset word 1 <15:8> 001 <39:32> phase offset word 1 <7:0> 001 <31:24> frequency tuning word 1 <31:24> 001 <23:16> frequency tuning word 1 <23:16> 001 <15:8> frequency tuning word 1 <15:8> 001 qduc profile 1 register (0fh) <7:0> frequency tuning word 1 <7:0> 001
preliminary technical data ad9957 rev. prf | page 27 of 38 register name (serial address) bit range (internal address) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 profile pins (ps2 - >ps0) <63:56> cci interpolation rate spectral invert inverse cci bypass 010 <55:48> output scale factor #2 010 <47:40> phase offset word #2 <15:8> 010 <39:32> phase offset word #2 <7:0> 010 <31:24> frequency tuning word #2 <31:24> 010 <23:16> frequency tuning word #2 <23:16> 010 <15:8> frequency tuning word #2 <15:8> 010 qduc profile 2 register (10h) <7:0> frequency tuning word #2 <7:0> 010 <63:56> cci interpolation rate spectral invert inverse cci bypass 011 <55:48> output scale factor #3 011 <47:40> phase offset word # 3 <15:8> 011 <39:32> phase offset word #3 <7:0> 011 <31:24> frequency tuning word #3 <31:24> 011 <23:16> frequency tuning word #3 <23:16> 011 <15:8> frequency tuning word #3 <15:8> 011 qduc profile 3 register (11h) <7:0> frequency tuning word #3 <7:0> 011 <63:56> cci interpolation rate spectral invert inverse cci bypass 100 <55:48> output scale factor #4 100 <47:40> phase offset word #4 <15:8> 100 <39:32> phase offset word #4 <7:0> 100 <31:24> frequency tuning word #4 <31:24> 100 <23:16> frequency tuning word #4 <23:16> 100 <15:8> frequency tuning word #4 <15:8> 100 qduc profile 4 register (12h) <7:0> frequency tuning word #4 <7:0> 100
ad9957 preliminary technical data rev. prf | page 28 of 38 register name (serial address) bit range (internal address) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 profile pins (ps2 - >ps0) <63:56> cci interpolation rate spectral invert inverse cci bypass 101 <55:48> output scale factor #5 101 <47:40> phase offset word # 5 <15:8> 101 <39:32> phase offset word #5 <7:0> 101 <31:24> frequency tuning word #5 <31:24> 101 <23:16> frequency tuning word #5 <23:16> 101 <15:8> frequency tuning word #5 <15:8> 101 qduc profile 5 register (13h) <7:0> frequency tuning word #5 <7:0> 101 <63:56> cci interpolation rate spectral invert inverse cci bypass 110 <55:48> output scale factor #6 110 <47:40> phase offset word #6 <15:8> 110 <39:32> phase offset word #6 <7:0> 110 <31:24> frequency tuning word #6 <31:24> 110 <23:16> frequency tuning word #6 <23:16> 110 <15:8> frequency tuning word #6 <15:8> 110 qduc profile 6 register (14h) <7:0> frequency tuning word #6 <7:0> 110 <63:56> cci interpolation rate spectral invert inverse cci bypass 111 <55:48> output scale factor #7 111 <47:40> phase offset word # 7 <15:8> 111 <39:32> phase offset word #7 <7:0> 111 <31:24> frequency tuning word #7 <31:24> 111 <23:16> frequency tuning word #7 <23:16> 111 <15:8> frequency tuning word #7 <15:8> 111 qduc profile 7 register (15h) <7:0> frequency tuning word #7 <7:0> 111
preliminary technical data ad9957 rev. prf | page 29 of 38 register name (serial address) bit range (internal address) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 profile pins (ps2 - >ps0) ram (16h) <31:0> ram [1023:0] <31:0> *** <63:56> open amplitude scale factor #0 <13:8> 000 <55:48> amplitude scale factor #0 <7:0> 000 <47:40> phase offset word #0 <15:8> 000 <39:32> phase offset word #0 <7:0> 000 <31:24> frequency tuning word #0 <31:24> 000 <23:16> frequency tuning word #0 <23:16> 000 <15:8> frequency tuning word #0 <15:8> 000 qduc single tone profile 0 register (0eh) <7:0> frequency tuning word #0 <7:0> 000 <63:56> open amplitude scale factor #1 <13:8> 001 <55:48> amplitude scale factor #1 <7:0> 001 <47:40> phase offset word #1 <15:8> 001 <39:32> phase offset word #1 <7:0> 001 <31:24> frequency tuning word #1 <31:24> 001 <23:16> frequency tuning word #1 <23:16> 001 <15:8> frequency tuning word #1 <15:8> 001 qduc single tone profile 1 register (0fh) <7:0> frequency tuning word #1 <7:0> 001 <63:56> open amplitude scale factor #2 <13:8> 010 <55:48> amplitude scale factor #2 <7:0> 010 <47:40> phase offset word #2 <15:8> 010 <39:32> phase offset word #2 <7:0> 010 <31:24> frequency tuning word #2 <31:24> 010 <23:16> frequency tuning word #2 <23:16> 010 <15:8> frequency tuning word #2 <15:8> 010 qduc single tone profile 2 register (10h) <7:0> frequency tuning word #2 <7:0> 010
ad9957 preliminary technical data rev. prf | page 30 of 38 register name (serial address) bit range (internal address) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 profile pins (ps2 - >ps0) <63:56> open amplitude scale factor #3 <13:8> 011 <55:48> amplitude scale factor #3 <7:0> 011 <47:40> phase offset word #3 <15:8> 011 <39:32> phase offset word #3 <7:0> 011 <31:24> frequency tuning word #3 <31:24> 011 <23:16> frequency tuning word #3 <23:16> 011 <15:8> frequency tuning word #3 <15:8> 011 qduc single tone profile 3 register (11h) <7:0> frequency tuning word #3 <7:0> 011 <63:56> open amplitude scale factor #4 <13:8> 100 <55:48> amplitude scale factor #4 <7:0> 100 <47:40> phase offset word #4 <15:8> 100 <39:32> phase offset word #4 <7:0> 100 <31:24> frequency tuning word #4 <31:24> 100 <23:16> frequency tuning word #4 <23:16> 100 <15:8> frequency tuning word #4 <15:8> 100 qduc single tone profile 4 register (12h) <7:0> frequency tuning word #4 <7:0> 100 <63:56> open amplitude scale factor #5 <13:8> 101 <55:48> amplitude scale factor #5 <7:0> 101 <47:40> phase offset word #5 <15:8> 101 <39:32> phase offset word #5 <7:0> 101 <31:24> frequency tuning word #5 <31:24> 101 <23:16> frequency tuning word #5 <23:16> 101 <15:8> frequency tuning word #5 <15:8> 101 qduc single tone profile 5 register (13h) <7:0> frequency tuning word #5 <7:0> 101
preliminary technical data ad9957 rev. prf | page 31 of 38 register name (serial address) bit range (internal address) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 profile pins (ps2 - >ps0) <63:56> open amplitude scale factor #6 <13:8> 110 <55:48> amplitude scale factor #6 <7:0> 110 <47:40> phase offset word #6 <15:8> 110 <39:32> phase offset word #6 <7:0> 110 <31:24> frequency tuning word #6 <31:24> 110 <23:16> frequency tuning word #6 <23:16> 110 <15:8> frequency tuning word #6 <15:8> 110 qduc single tone profile 6 register (14h) <7:0> frequency tuning word #6 <7:0> 110 <63:56> open amplitude scale factor #7 <13:8> 111 <55:48> amplitude scale factor #7 <7:0> 111 <47:40> phase offset word #7 <15:8> 111 <39:32> phase offset word #7 <7:0> 111 <31:24> frequency tuning word #7 <31:24> 111 <23:16> frequency tuning word #7 <23:16> 111 <15:8> frequency tuning word #7 <15:8> 111 qduc single tone profile 7 register (15h) <7:0> frequency tuning word #7 <7:0> 111
ad9957 preliminary technical data rev. prf | page 32 of 38 register descriptions control function register #1 (cfr1) the cfr1 is comprised of four bytes located in address 00h cfr1<31> : ram enable bit . when cfr1<31> = 0 (default), disables the ra putting it in the lowest power state (unless being written to via the serial port). hen cfr1<31> = 1, enables the ram. cfr1<30:29> : open . always leave these bits clear. cfr1<28> : ram qduc evaluation enable bi t. when cfr1<28> = 0 (default) , the ra qduc evaluation mode of the device is inactive. hen cfr1<28> = 1, the ram qduc evaluation mode is activated, if the ram enable bit is set. when in the ram qduc evaluation mode the input data port is disengaged form the signal processing path and the ram drives the i and q data at the iq sample rate. cfr1<27:26> : open . always leave these bits clear. cfr1<25:24> : qduc operating mode bits . the cfr1<25:24> bits set the mode of operation: cfr1<25:24> mode of operation 00 ( default ) quadrature odulation 0 single tone x interpolating dac cfr1<23> : manual osk external control . note, this bit is ignored unless manual osk mode is se- lected using cfr1<9:8>. when cfr1<23> = 0 (default) , the manual osk mode does not require the use of the osk input pin to operate. hen cfr1<23> = 1, the manual osk mode uses the osk input pin. see pin description. cfr1<22> : inverse sinc enable bit . when cfr1<22> = 0 (default) , the inverse sinc filter is inactive - the local clock is stopped to save power. the input data is passed directly to the output of the filter. hen cfr1<22> = 1, the inverse sinc filter is enabled and operational. cfr1<21> : clear cci bit . when cfr1<21> = 0 (default) , the cci filter operates normally. hen cfr1<21> = 1, the cci filter is asynchronously cleared. cfr1<20:17> : internal profile control bits . these bits cause the profile bits to be ignored and put the device into an automatic profile loop sequence that allows the user to implement a frequency/phase compos- ite sweep that runs without external inputs. cfr1<16> : sine enable bit . when cfr1<16> = 0 (default) , the angle-to-amplitude conversion logic outputs a cosine function. hen cfr , the angle-to-amplitude conver- sion logic outputs a sine function. cfr1<15:14> : open . always leave these bits clear. cfr1<13>: auto clear phase accumulator when cfr1<13> = 0 (default) , ) , the accumulation function is not interrupted. hen cfr3 , this bit automatically and syn- chronously clears (loads eros into) the phase accumula- tor for one cycle upon receipt of the io update se- quence indicator. cfr1<12>: open . always leave this bit clear. cfr1<11>: clear phase accumulator when cfr1<11> = 0 (default) , the phase accumulator functions as normal. hen cfr , the phase accumulator memory element is asynchronously cleared. cfr1<10> : load amplitude rate register @ ioupdate when cfr1<10> = 0 (default) , the amplitude ramp rate timer is loaded only upon timeout (timer ) it is not loaded due to an io update input signal (or change in profile). hen cfr0 , the amplitude ramp rate timer is loaded upon timeout (timer ) or at the time of an io update input signal (or change in profile). cfr1<9> : output shaped keying enable
preliminary technical data ad9957 rev. prf | page 33 of 38 cfr1<9> = 0 ( default ), disables shaped on-off keying. the clocks to this function are stopped for power sav- ings. cfr9 , enables shaped on-off keying. cfr8 sets the mode of operation. cfr1<8> : automatic output shaped keying enable if cfr1<9> is clear, this bit is ignored. cfr1<8> = 0 enables manual shaped on-off keying. cfr1<8> = 1 enables auto shaped on-off keying. cfr1<7> : digital power down cfr1<7> = 0 ( default ), enables the digital circuitry. cfr7 , disables the digital circuitry, putting it in its lowest power dissipation state. cfr1<6> : dac power down cfr1<6> = 0 ( default ), enables the dac circuitry. cfr , disables the dac circuitry, putting it in a low power dissipation state. cfr1<5> : clock input power down cfr1<5> = 0 ( default ), enables the clock input cir- cuitry. cfr5 , disables the clock input circuitry putting it in a low power dissipation state. cfr1<4> : open cfr1<3> : external power down mode when cfr1<3> = 0 (default) the external power down mode selected is fast recovery power down. in this mode, when the etprdn input pin is high, the digital logic and the dac digital logic are powered down. the dac bias circuitry, comparator, pll, oscilla- tor, and clock input circuitry is not powered down. hen cfr3 , the external power down mode se- lected is full power down. in this mode, when the etprdn input pin is high, all functions are pow- ered down including the dac and pll, which take a significant amount of time to power up. cfr1<2>: automatic power down cfr1<2> = 0 ( default ), disables automatic power down. hen cfr2 when t enable is de-asserted for a sufficiently long period of time the device auto- matically switches into its low power mode. cfr1<1>: sdio input only cfr1<1> = 0 ( default ), configures the sdio pin for bi- directional operation (2-wire serial programming mode). cfr , configures the serial data io pin (sdio) as an input only pin (3-wire serial programming mode). cfr1<0>: lsb first cfr1<0> = 0 ( default ), sets sb first format. cfr0 , sets lsb first format. control function register #2 (cfr2) cfr2<31> : blackfin interface mode active bit . when cfr2<31> = 0 (default), the parallel input data port operates as described in the data assembler section of this document. hen cfr2<31> = 1, the ad9957 data port is config- ured for direct connection to the blackfin sport inter- face . see the blackfin interface section of this document for details. cfr2<30> : blackfin bit order bit . this bit is ignored if the ad9957 is not operating in the blackfin interface mode (see cfr2<31>). cfr2<30> = 0 (default) sets sb first format. cfr2<30> = 1 sets lsb first format. cfr2<29> : blackfin early frame sync enable bit . this bit is ignored if the ad9957 is not operating in the blackfin interface mode (see cfr2<31>). when cfr2<29> = 0 (default) , the frame sync signal is expected by the ad9957 to be co-incident with the first data bit transmitted. (late frame sync operation in the blackfin documentation). hen cfr2<29> = 1, the frame sync signal is expected by the ad9957 to be one cycle preceding the first data bit transmitted. (early frame sync operation in the blackfin documentation). also, for continuous data transmission, the early frame sync bit will be co-incident with the last bit of the previous word transmitted. cfr2<28:25>: open . leave these bits clear cfr2<24> : single tone profile enable bit . when cfr2<24> = 0 (default) , direct modulation of
ad9957 preliminary technical data rev. prf | page 34 of 38 amplitude via the profile registers is not possible. when cfr2<24> = 1, direct modulation of amplitude via the profile registers is possible, depending upon other chip configurations. cfr2<23> : internal io update active bit . when cfr2<23> = 0 (default) , the io update feature is controlled externally through the ioupdate pin, which is configured as an input.. hen cfr2<23> = 1, the io update feature is controlled internally via a down counter. the i/o_update pin, is configured as an output to signal the user to when io up- dates have occurred. cfr2<22> : enable io sync clk bit . cfr2<22> = 1 (default) , activates the iosncclk pin. hen cfr2<22> = 0, the iosyncclk pin is pulled low. cfr2<21:17> : open . always leave these bits clear. cfr2<16> : read effective ftw bit when cfr2<16> = 0 (default, a serial io read instruc- tion reads hex address 07h (ft register), the serial port reads back the register at hex address 07h. hen cfr2<16> = 1, a serial io read instruction reads hex address 07h (ftw register), the serial port reads back the active ftw. cfr2<15:14> : io update rate control bits . these bits are ignored if internal io update is not activated using bit cfr2<23> the cfr2<15:14> bits set the clock rate for the io up- date down counter. the table below indicates the clock rate divisor cfr2<15:14> io sync clk divisor 00 1 01 2 10 4 11 8 cfr2<13> : pdclk rate control bit . when cfr2<13> = 0 (default), the rate out of the pdclk pin is equal to the input data rate. hen cfr2<13> = 1, the rate out of the pdclk pin is equal to one half the input data rate. this provides in- sight into the phase of the signal processing clock, rela- tive to the input data rate. see the data assembler sec- tion of the functional description for details. cfr2<12> : data format bit . when cfr2<12> = 0 (default) , data received is treated as twos complement. hen cfr2<12> = 1, data received is treated as offset binary. the msb of the data word is inverted before be- ing sent to the signal processing logic. cfr2<11> : enable pdclk bit cfr2<11> = 0 pulls the pdclk pin low. cfr2<11> = 1 (default) activates pdclk pin. cfr2<10> : pdclk invert bit when cfr2<10> = 0 (default) , the pdclk pin is in phase with the clock that samples the data into the part. hen cfr2<10> = 1, the pdclk pin is in inverted from the clock that samples the data into the part. cfr2<9> : txenable invert bit when cfr2<9> = 0 (default) , a logic on the txenable pin indicates i data and a logic 0 on the txenable pin indicates q data, if the user is employing a continuous timing style on the txenable pin. for burst timing style, if the txenable in- vert bit is cleared, a logic on the txenable pin enables the ad9957 to transmit data and a logic ero indicates no fur- ther data is to be transmitted. hen cfr2<9> = 1, a logic 1 on the txenable pin indi- cates q data and a logic 0 on the txenable pin indicates i data, if the user is employing a continuous timing style on the txenable pin. for burst timing style, if the txenable in- vert bit is set, a logic 0 on the txenable pin enables the ad9957 to transmit data and a logic one indicates no fur- ther data is to be transmitted. cfr2<8> : q first data pairing bit when cfr2<8> = 0 (default) , i data precedes q data in the assembly of the iq data pair that is processing in the qduc signal chain. hen cfr2<8> = 1, q data precedes i data in the assembly of the i/q data pair that is processing in the qduc signal chain. cfr2<7> : matched latency bit .
preliminary technical data ad9957 rev. prf | page 35 of 38 when cfr2<7> = 0 (default) , the frequency tuning ord, phase offset and amplitude scalar pipe delays are mini- mied. the output will reflect amplitude changes before it reflects phase changes, and phase changes before it reflects frequency changes. hen cfr2<7> = 1, the frequency tuning word, phase offset and amplitude scalar pipe delays are implemented such that the simultaneous application of changes in fre- quency, phase and amplitude are reflected on the output si- multaneously too. cfr2<6> : data assembler holds last value bit when cfr2<6> = 0 (default) , the data port drives logic e- ros onto the signal processing data path when transmission is disabled. hen cfr2<6> = 1, the data port holds the last data word registered when transmission is disabled. cfr2<5> : sync sample error mask bit cfr2<5> = 0 disables the sync_smp_err pin. cfr2<5> = 1 (default) enables the sncsperr pin. cfr2<3:0> : fm gain bits . when operating the device in single tone mode and fm modulation is selected via the data port destination bits, if the single tone data port enable bit is set, these bits are used to select one of 16 possible 16-bit ranges relative to the 32-bit dds tuning word . control function register #3 (cfr3) cfr3<31:30> : drv0 (xtal_out) control bits. these bits set the drive strength of the buffered reference clock output on pin 93. 00 = off (default) 0 low drive strength 0 id drive strength high drive strength cfr3<29:27> : open . leave these bits clear. cfr3<26:24> : vco selection bits. as per the table below, these bits set the vco for the appro- priate range. bits min max 000 420mhz 485mhz 001 485mhz 560mhz 010 560mhz 655mhz 011 655mhz 830mhz 100 830mhz 920mhz 101 920mhz 1000mhz 11x pll will not function cfr3<21:19> : charge pump current bits as per the table below, these bits set the charge pump output current. cfr3<21:19> charge pump current ( a) 000 200 001 225 010 250 011 275 100 300 101 325 110 350 111 375 table 6 charge pump output current settings cfr3<18:16> : open . leave these bits clear cfr3<15> : refclk input divider disable bit. when cfr3<15> = 0 the ad9957 refclk input divider is bypassed. the internal sysclk fed to the device (or the clock multiplier) equals the refclk rate when cfr3<15> = 1 (default) the ad9957 refclk input divider is enabled (to 2). the internal sysclk fed to the de- vice (or the clock multiplier) is equal to the refclk rate. cfr3<14> : open this bit is used strictly for testing, leave set. cfr3<13:9> : open these bits are used for testing leave clear. cfr3<8> : pll enable bit. when cfr3<8> = 0 (default). the ad9957 reference clock rate equals the dac clock sampling rate. the pll is by- passed and the clock multiplier is powered down. hen cfr3<8> = 1, the ad9957 reference clock rate times the pll multiplier bit (integer equivalent) equals the dac clock sampling rate. cfr3<7:1 >: refclk multiplier bits. these bits make up the 8-bit word that is the multiplication factor used by the pll clock multiplier circuitry. the decimal equivalent of the binary value of these bits is the multiplication factor. only certain values are valid (see ta-
ad9957 preliminary technical data rev. prf | page 36 of 38 ble 4). if the pll is enabled (cfr3<8>), a valid value must be programmed here for proper pll operation. if the pll is disabled, these bits are ignored. cfr3<0> : refclk input doubler active bit when cfr3<0> = 0 (default) the reference clock is fed di- rectly to the pfd. hen cfr3<0> = 1, the reference clock is doubled in fre- quency prior to being fed to the pfd. auxilliary dac control register these bits control the auxiliary dac that modulates the full scale current of the tx dac for a default dac_rset value of 10k, these bits modulate the dac output full scale current be- teen ma and 31ma, ith each lsb representing ap- proximately 0a of resolution io update rate register this register sets the interval for the don counter hich di- vides the system cloc don to an internal i/o update interval period when the internal i/o update mode is disabled, this register is ignored each lsb represents one snc_clk cycle, so the interval for an internal i/o update rate varies beteen 1 and 232( 4,24,,2) sync_cloc cycles, here a sync_cloc cycle is of a system cloc cycle qduc ram segment registers (qrsr0, qrsr1) these registers program the behavior of the internal ram con- troller for hen the ram is configured to drive qduc data or drive the input scalars qrsr0 feeds data to the i-channel and qrsr1 feeds data to the q-channel these registers serve no function hen the ad is prog rammed to be in single-tone mode qrsrx<47:32> ram segment address ramp rate this 16 bit word controls the period between qduc ram segment steps. each lsb in this word weights the delay by 1 sync_clk cycle (which is the sys- tem clock rate). qrsrx<31:22> ram segment final address this 10 bit word specifies the final address location in the ram where the data profile is stored. qrsrx<21:16> open qrsrx<15:6> ram segment beginning address this 10 bit word specifies the beginning address loca- tion in the ram where the data profile is stored. qrsrx<5:3> open qsrx<2:0> ram segment mode control this 3 bit word specifies the behavior the ram con- troller follows when stepping through the segment ac- cording to the following table. note, the behavior in- dicated refers to the ram address itself, not necessar- ily the data stored and sent to the qduc. qsrx<2:0> ram mode 000 direct switch (beginning address only) 001 ramp up 010 bidirectional ramp (ramp up, ramp down) 011 continuous bidirectional (ramp up, ramp down, ramp up, etc) 100 continous recirculate (ramp up from beginning to final address, then immediately return to beginning address and repeat). 101, 110, 111 not used frequency tuning word register (ftw) this register sets the frequency tuning ord of the dds core, hich is either the output frequency (single tone mode) or the carrier frequency (modulator mode) when the phase/frequency/amplitude profiles are enabled, this register serves no function phase offset word register (pow) this register controls the phase offset of the dds core in either the output frequency (single tone mode) or the carrier fre- quency (modulator mode) when the phase/frequency/amplitude profiles are enabled, this register serves no function amplitude scale factor (asf) this register controls the digital multiplier (amplitude scale factor) inside the dds core itself it does not affect the digital multiplier immediately prior to the dac in automatic osk mode, this controls the ramp rate and final value of the ampli- tude ramping function in manual osk mode, only the ampli- tude scale factor is used, the amplitude ramp rate is dont care when the phase /frequency /amplitude profiles are en- abled, this register serves no function qduc profile x register (qduc-pxr)/ single tone profile x register (st-pxr) there are special purpose registers hich reside at addresses h0e to h1 these registers can tae on one of three roles they can either be qduc profile registers, ram profile registers or single tone profile registers
preliminary technical data ad9957 rev. prf | page 37 of 38 first and foremost, the part will use these registers as qduc profile registers if the part is in quadrature modulator mode cfr1<25:24> = 00.
ad9957 preliminary technical data rev. prf | page 38 of 38 outline dimensions compliant to jedec standards ms-026-aed-hd 1 25 26 50 76 100 75 51 14.00 bsc sq 16.00 bsc sq 0.75 0.60 0.45 1.20 max 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw seating plane 0 min 7 3.5 0 0.15 0.05 view a pin 1 top view (pins down) 0.27 0.22 0.17 0.50 bsc lead pitch 1 25 26 50 76 100 75 51 bottom view (pins up) 5.00 sq exposed pad notes 1. center figures are typical unless otherwise noted. 2. the ad9957 has a conductive heat slug to help dissipate heat and ensure reliable operation of the device over the full industrial temperature range. the slug is exposed on the bottom of the package and electrically connected to v ee . it is recommended that no pcb signal traces or vias be located under the package that could come in contact with the conductive slug. attaching the slug to a v ee plane will reduce the junction temperature of the device which may be beneficial in high temperature environments. 080106-a ordering guide model temperature range package description package outline ad9957bsvz C40c to +105c 48-lead thin plastic quad flat package, exposed pad (tqfp_ep) ad9957bsvz- reel13 C40c to +105c 48-lead thin plastic quad flat pa ckage, exposed pad (tqfp_ep), 1000 device, 13-inch reel ad9957/pcbz evaluation board

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